//==============================================================================
//
//  File        : mmp_register_dma.h
//  Description : INCLUDE File for the Retina register map.
//  Author      : Rogers Chen
//  Revision    : 1.0
//
//==============================================================================



#ifndef _MMP_REG_AUDIO_H_
#define _MMP_REG_AUDIO_H_

#include    "mmp_register.h"

/** @addtogroup MMPH_reg
@{
*/


// ********************************
//   Audio structure (0x8000 7800)
// ********************************
typedef struct _AITS_AUD {
    AIT_REG_B   I2S_FIFO_CPU_INT_EN;                                     // 0x0
    AIT_REG_B   I2S_FIFO_HOST_INT_EN;      								 // 0x1
        /*-DEFINE-----------------------------------------------------*/
        #define AUD_INT_FIFO_EMPTY             0x0001
        #define AUD_INT_FIFO_FULL              0x0002
        #define AUD_INT_FIFO_REACH_UNRD_TH     0x0004
        #define AUD_INT_FIFO_REACH_UNWR_TH     0x0008
		/*------------------------------------------------------------*/    
	AIT_REG_W   						_x02;
    AIT_REG_B   I2S_FIFO_SR;                                         	 // 0x4
	AIT_REG_B   						_x05[3];
    AIT_REG_B   I2S_FIFO_RST;                                         	 // 0x8
        /*-DEFINE-----------------------------------------------------*/
		#define AUD_FIFO_RST_EN                0x0001
		/*------------------------------------------------------------*/    

	AIT_REG_B   						_x09[3];
    #if (CHIP == P_V2)||(CHIP == VSN_V2)
    AIT_REG_D   I2S_FIFO_DATA;                                           // 0x0C
    #endif
	AIT_REG_W   I2S_FIFO_RD_TH;                                          // 0x10
	AIT_REG_W   						_x12;
	AIT_REG_W   I2S_FIFO_WR_TH;                                          // 0x14
	AIT_REG_W   						_x16;
	AIT_REG_W   I2S_FIFO_UNRD_CNT;                                       // 0x18
	AIT_REG_W   						_x1A;
	AIT_REG_W   I2S_FIFO_UNWR_CNT;                                       // 0x1C
	AIT_REG_W   						_x1E[5];                         
	AIT_REG_B   I2S_CTL;                                                 // 0x28
        /*-DEFINE-----------------------------------------------------*/
		#define I2S_SDO_OUT_EN                 0x08
		#define I2S_LRCK_OUT_EN                0x04
		#define I2S_BCK_OUT_EN                 0x02
		#define I2S_HCK_CLK_EN                 0x01
		#define I2S_ALL_DIS                    0x0
		/*------------------------------------------------------------*/    
	AIT_REG_B   						_x29[3];
	AIT_REG_B   I2S_CLK_DIV;                                             // 0x2C
	AIT_REG_B   I2S_MCLK_FIXMODE;                                        // 0x2D
	AIT_REG_W   						_x2E;
	AIT_REG_W   I2S_RATIO_N_M;                         					 // 0x30
	AIT_REG_W   						_x32;
	AIT_REG_B   I2S_BIT_CLT;                                             // 0x34
	AIT_REG_B   						_x35[3];
	AIT_REG_B   I2S_LRCK_POL;                                            // 0x38
	AIT_REG_B   						_x39[3];
    #if (CHIP == P_V2)||(CHIP == VSN_V2)
    AIT_REG_D   I2S_L_CHNL_DATA;                                        // 0x3C
    AIT_REG_D   I2S_R_CHNL_DATA;                                        // 0x40
    #endif
    #if (CHIP == VSN_V3)
    AIT_REG_B	I2S_BIT_ALIGN_OUT;										// 0x44
    #elif (CHIP == VSN_V2)
    AIT_REG_B							_x44;
    #endif
    
	AIT_REG_B   I2S_BIT_ALIGN_IN;      								 	 // 0x45
	AIT_REG_W   						_x46;
	AIT_REG_B   I2S_MODE_CTL;                                           // 0x48
        /*-DEFINE-----------------------------------------------------*/
		#define I2S_MCLK_OUT_EN                 4
		#define I2S_SLAVE                       0   
		#define I2S_MASTER                      1   
		/*------------------------------------------------------------*/    
	AIT_REG_B   						_x49[3];
	AIT_REG_B   I2S_MCLK_CTL;	      									// 0x4C
        /*-DEFINE-----------------------------------------------------*/
    	#define I2S_384_FS				 0x08
    	#define I2S_256_FS				 0x04
    	#define I2S_192_FS				 0x02								 	 
    	#define I2S_128_FS				 0x01							
		/*------------------------------------------------------------*/    
	AIT_REG_B   						_x4D[3];
	AIT_REG_B   I2S_ASPORT_CTL;	      								 	 // 0x50
        /*-DEFINE-----------------------------------------------------*/
    	#define I2S_ASPORT_EN			 0x01							
		/*------------------------------------------------------------*/
	AIT_REG_B							_x51[7];							//0x51
	AIT_REG_B   I2S_DATA_IN_SEL;										 // 0x58
        /*-DEFINE-----------------------------------------------------*/
        #define I2S_SDO_IN     				    0x01
        #define I2S_SDI_IN    				    0x00
		/*------------------------------------------------------------*/    
	AIT_REG_B   						_x59[3];
    AIT_REG_B   I2S_CPU_INT_EN;                                          // 0x5C
    AIT_REG_B   I2S_HOST_INT_EN;                                         // 0x5D
        /*-DEFINE-----------------------------------------------------*/
        #define AUD_INT_EN     				    0x01
        #define AUD_INT_DIS    				    0x00
		/*------------------------------------------------------------*/    
	AIT_REG_B   						_x5E[14];
	
	AIT_REG_B	I2S_INT_CLR;											// 0x6C
	AIT_REG_B							_x6D[3];
	AIT_REG_B	I2S_MUX_MODE_CTL;										// 0x70
        /*-DEFINE-----------------------------------------------------*/
        #define AUD_MUX_AUTO			    	0x01
        #define AUD_MUX_CPU			    		0x00
		/*------------------------------------------------------------*/
	} AITS_AUD, *AITPS_AUD;

////////////////////////////////////
// Register definition
//

#if !defined(BUILD_FW)
#endif


/// @}

#endif // _MMP_REG_AUDIO_H_
